With the rapid development of semiconductor manufacturing technology, the technical node of the semiconductor technology has been continuously shrunk by following the Moore's Law. To adapt to the reduced technical node, the channel length of the MOSFETs has to be continually reduced. Reducing the channel length of the MOSFETs is able to increase the device density of the integrate circuits (ICs); and increase the switching speed of the MOSFETs, etc.
However, with the continuously shrinking the channel length, the distance between the source and the drain of the device has also be correspondingly reduced. Accordingly, the control ability of the gate on the channel region is reduced; and the difficulty for the gate voltage to pinch off the channel region is increased. Thus, the subthreshold leakage phenomenon may occur. That is, it may be easier to have the short channel effects (SCEs).
Thus, to meet the miniaturization requirements of the semiconductor devices, the semiconductor technology has been gradually developed from the planar MOSFETs to the three-dimensional transistors that have better performances. Fin field-effect transistors (FinFETs) are a typical type of three-dimensional devices.
In a FinFET, the gate is able to control the ultrathin components (i.e., fins) from at least two sides. Thus, comparing with a planar MOSFET, the gate of the FinFET has a stronger control ability on the channel region; and may be able to effectively inhibit the SCEs. Further, comparing with other devices, FinFETs have better compatibilities with the existing IC manufacturing technologies.
However, in the existing technologies, when fins with different critical dimensions (CDs) need to be formed in the FinFET, the fabrication processes may be relatively complex. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems in the art.